The present invention relates to an image display device which is arranged to display an image composed of video signals in synchronization with the timing of a dot clock generated by a horizontal synchronizing (sync) signal for driving the imaging device.
As disclosed in JP-A-7-160222, there has been conventionally known a liquid crystal display device which is arranged to display an image in response to video signals for driving a CRT display device supplied from a personal computer, a workstation, a VTR or the like.
The liquid crystal display device (LCD) disclosed in the JP-A-7-160222 is arranged as shown in a block diagram of FIG. 13. That is, a video signal R101 (Red), a video signal G102 (Green), and a video signal B103 (Blue) for driving a CRT display device are converted into the digital image data 106, 107, and 108 through the effect of A/D converting circuits 10, 11 and 12 each serving as an analog-to-digital (A/D) converting means and then the resulting digital image data are outputted into a display control circuit 13. The display control circuit 13 is input with the digital image data 106, 107 and 108, the dot clock 109, a horizontal sync signal 104, and a vertical sync signal 105. The circuit serves to convert those signals into those of the formats adapted for the liquid crystal display unit 14 and then display the image on the LCD unit 14.
On the other hand, a variable delay generating circuit 9 operates to properly delay the horizontal sync signal 104 and then output the delayed signal as a delayed horizontal sync signal 110 into a PLL circuit (Phased Loop Lock) 15 serving as means for generating the dot clock.
The PLL circuit 15 operates to generate the corresponding dot clock 109 to the pixels in synchronization with the delayed horizontal synchronous signal 110 and then output the dot clock 109 as the conversion timing signal for the A/D converting circuits 10, 11 and 12. If the delay of the variable delay generating circuit 9 is changed, the phase of the clock 109 generated in synchronization with the signal 110 is changed accordingly. The delayed horizontal sync signal 110 outputted from this variable delay generating circuit 9 is subject to the following adjustment. The phase of the dot clock 109 is changed so that the sampling timings of the A/D converting circuits 10, 11 and 12 are located on the centers of the analog video signals 101, 102 and 103. The adjustment of the variable delay generating circuit 9 will be described below with reference to FIGS. 14A-14G.
FIGS. 14A and 14C show signals output from a personal computer or a workstation. Specifically, the signal shown in FIG. 14A denotes a horizontal sync signal 104 and the signal shown in FIG. 14C denotes an analog video signal R101. This holds true to the other analog video signals G101 and B103. Hence, the concrete signals about the other analog video signals are left out. FIG. 14B shows the dot clock outputted from the PLL circuit 15. FIGS. 14D to 14G show the dot clock 109 and the video signal R101 expanded toward the time axis. In FIG. 14E, a waveform B shown in a real line denotes an analog video signal R101 outputted from a personal computer or a workstation. If the secured frequency band of this analog video signal R101 is high enough, the analog video signal R101 is made to take a waveform A shown by a broken line. Actually, the analog video signal is made to take the waveform B shown by a real line because the high frequency characteristics of the video output circuit and a transmission cable are degraded.
Herein, FIG. 14D shows the dot clock generated if the variable delay generating circuit 9 is not properly adjusted. In this case, as shown in FIG. 14E, focusing on an S1 point, a sampled portion is not the peak of the obtuse waveform B. Hence, the S1 point takes a different value from the value to be given if the waveform A is sampled, so that an error shown by Ve takes place. This error causes the contrast on the display to be degraded.
On the other hand, FIG. 14F shows the dot clock to be given if the variable delay generating circuit 9 is properly adjusted. In this dot clock, as shown in FIG. 14G, the peak of the obtuse waveform B is sampled. Hence, this sampling gives rise to the same digital data value as the value to be given if the waveform A is sampled. This makes it possible to avoid degrading of the display quality such as degraded contrast.
The disadvantages of the conventional image display device arranged as shown in FIG. 13 will be described below with reference to FIGS. 15A-15D. FIG. 15A shows the dot clock 109 described with reference to FIG. 13. FIGS. 15B to 15D show the analog video signals R101, G102 and B103 outputted from a personal computer or a workstation. The dot clock 109 shown in FIG. 15A takes a phase given if the adjustment of the variable delay generating circuit 9 is properly done with respect to the analog video signal R101 shown in FIG. 15B. In this case, as described with reference to FIGS. 14A-14G, an SR point, that is, a peak of the analog video signal waveform is sampled. This sampling gives rise to the same digital data value as the value to be given if an ideal square waveform is sampled. This results in avoiding the degrading of the display quality such as degraded contrast.
Actually, however, the analog video signal outputted from a personal computer or a workstation disadvantageously includes skew among the Red, the Green and the Blue video signals because of a variety of characteristics of the image output circuits and the transmission cables located inside of the personal computer or the workstation. In FIGS. 15A-15D, for the purpose of making the description easier, the Red, the Green and the Blue signals have the same waveforms except their skews. If this analog video signal G102 and the video signal B103 are sampled through the use of the dot clock 109 shown in FIG. 15A, the analog video signals G102 and B103 are sampled at the SG and the SB points. It means that the sampled results have the errors VeG and VeB as compared with the values to be given by sampling the ideal square waveforms.
These errors make the relation among the Red, the Green and the Blue out of balance, thereby causing color blur. Therefore, if the analog video signals have skews among the Red, the Green and the Blue, whatever kind of adjustment the variable delay generating circuit 9 may be performed, the same digital data values as those to be given by sampling the ideal square waveforms cannot be obtained with respect to all of the colors, the Red, the Green and the Blue. This kind of disadvantage is remarkable in high-resolution image display devices in which the dot clock 109 has a high frequency.